1. Field of the Invention
The present invention relates generally to analog to digital converters (ADC), and more specifically to a technique to correct for errors that cause generated digital codes to deviate from expected values in an ADC.
2. Related Art
Analog to digital converters (ADCs) are used to generate a sequence of digital codes representing the strength of an analog signal at corresponding time instances, and may be implemented according to various techniques such as successive approximation (SAR) ADC, pipelined ADC, etc., as is well known in the relevant arts.
ADCs are generally designed to generate a specific value (“expected value”) for a given strength of an analog signal (at the sample time instance). Typically, the ADC is designed to process input signals with a range of strength (often referred as a “dynamic range” of the ADC), and a specific sub-range of strength is associated with each digital code that can be generated by the ADC. The digital code is generally the expected code for the corresponding sub-range of strength.
The digital codes generated by an ADC may deviate from the expected values due to reasons such as non-linearity of various components of an ADC, offset/gain errors, etc., as is well known in the relevant arts. It is generally desirable that the generated digital codes equal the expected values.